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» Hardware efficient architectures for Eigenvalue computation
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APCSAC
2003
IEEE
15 years 3 months ago
Arithmetic Circuits Combining Residue and Signed-Digit Representations
This paper discusses the use of signed-digit representations in the implementation of fast and efficient residue-arithmetic units. Improvements to existing signed-digit modulo adde...
Anders Lindström, Michael Nordseth, Lars Beng...
DAC
2004
ACM
15 years 10 months ago
A recursive paradigm to solve Boolean relations
A recursive algorithm for solving Boolean relations is presented. It provides several features: wide exploration of solutions, parametrizable cost function and efficiency. The exp...
David Bañeres, Jordi Cortadella, Michael Ki...
DAC
2004
ACM
15 years 10 months ago
Dynamic FPGA routing for just-in-time FPGA compilation
Just-in-time (JIT) compilation has previously been used in many applications to enable standard software binaries to execute on different underlying processor architectures. Howev...
Roman L. Lysecky, Frank Vahid, Sheldon X.-D. Tan
FPGA
2004
ACM
163views FPGA» more  FPGA 2004»
15 years 1 months ago
Time and area efficient pattern matching on FPGAs
Pattern matching for network security and intrusion detection demands exceptionally high performance. Much work has been done in this field, and yet there is still significant roo...
Zachary K. Baker, Viktor K. Prasanna
VLSID
2005
IEEE
167views VLSI» more  VLSID 2005»
15 years 10 months ago
A Methodology and Tooling Enabling Application Specific Processor Design
This paper presents a highly efficient processor design methodology based on the LISA 2.0 language. Typically the architecture design phase is dominated by an iterative processor ...
Andreas Hoffmann, Frank Fiedler, Achim Nohl, Suren...