421 search results - page 50 / 85 » Hardware efficient architectures for Eigenvalue computation |
DAC
2008
ACM
15 years 10 months ago
2008
ACM
In this paper, we present ELIAD, an efficient lithography aware detailed router to optimize silicon image after optical proximity correction (OPC) in a correct-by-construction man...
112
click to vote
CODES
2006
IEEE
15 years 3 months ago
2006
IEEE
The memory subsystem of a complex multiprocessor systemson-chip (MPSoC) is an important contributor to the chip power consumption. The selection of memory architecture, as well as...
SIGCOMM
2010
ACM
14 years 10 months ago
2010
ACM
Traditionally, in-network services like firewall, proxy, cache, and transcoders have been provided by dedicated hardware middleboxes. A recent trend has been to remove the middleb...
ISCAS
2007
IEEE
15 years 4 months ago
2007
IEEE
— This paper describes the hardware architecture for a flexible probability density estimation unit to be used in a Large Vocabulary Speech Recognition System, and targeted for m...
VLSID
2001
IEEE
15 years 10 months ago
2001
IEEE
In this paper, we propose a new transparent built-in self-test ( TBIST ) method to test multiple embedded memory arrays with various sizes in parallel. First, a new transparent tes...