Sciweavers

421 search results - page 54 / 85
» Hardware efficient architectures for Eigenvalue computation
Sort
View
DSD
2005
IEEE
116views Hardware» more  DSD 2005»
15 years 3 months ago
Optimization of a Bus-based Test Data Transportation Mechanism in System-on-Chip
The increasing amount of test data needed to test SOC (System-on-Chip) entails efficient design of the TAM (test access mechanism), which is used to transport test data inside the...
Anders Larsson, Erik Larsson, Petru Eles, Zebo Pen...
MICRO
2010
IEEE
119views Hardware» more  MICRO 2010»
14 years 7 months ago
A Predictive Model for Dynamic Microarchitectural Adaptivity Control
Abstract--Adaptive microarchitectures are a promising solution for designing high-performance, power-efficient microprocessors. They offer the ability to tailor computational resou...
Christophe Dubach, Timothy M. Jones, Edwin V. Boni...
VR
2000
IEEE
172views Virtual Reality» more  VR 2000»
15 years 2 months ago
An Intelligent User Interface with Motion Planning for 3D Navigation
Due to the rapid evolution of graphics hardware, interactive 3D graphics is becoming popular on desktop personal computers. However, it remains a challenging task for a novice use...
Tsai-Yen Li, Hung-Kai Ting
ICRA
1994
IEEE
127views Robotics» more  ICRA 1994»
15 years 1 months ago
"RISC" for Industrial Robotics: Recent Results and Open Problems
At the intersection of robotics, computational geometry, and manufacturingengineering, we have identifieda collection of research problems with near-term industrial applications. ...
John F. Canny, Kenneth Y. Goldberg
ISLPED
1995
ACM
112views Hardware» more  ISLPED 1995»
15 years 1 months ago
Ultra-low-power analog associative memory core using flash-EEPROM-based programmable capacitors
Analog techniques can lead to ultra-efficient computational systems when applied to the right applications. The problem of associative memory is well suited to array-based analog ...
Alan Kramer, Roberto Canegallo, Mauro Chinosi, D. ...