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» Hardware efficient architectures for Eigenvalue computation
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DAC
2009
ACM
15 years 1 months ago
Reduction techniques for synchronous dataflow graphs
The Synchronous Dataflow (SDF) model of computation is popular for modelling the timing behaviour of real-time embedded hardware and software systems and applications. It is an es...
Marc Geilen
IEEEPACT
2005
IEEE
15 years 3 months ago
Exploiting Coarse-Grained Parallelism to Accelerate Protein Motif Finding with a Network Processor
While general-purpose processors have only recently employed chip multiprocessor (CMP) architectures, network processors (NPs) have used heterogeneous multi-core architectures sin...
Ben Wun, Jeremy Buhler, Patrick Crowley
DAC
2008
ACM
15 years 10 months ago
Compiler-driven register re-assignment for register file power-density and temperature reduction
Temperature hot-spots have been known to cause severe reliability problems and to significantly increase leakage power. The register file has been previously shown to exhibit the ...
Xiangrong Zhou, Chenjie Yu, Peter Petrov
SIGMETRICS
2000
ACM
111views Hardware» more  SIGMETRICS 2000»
14 years 9 months ago
AMVA techniques for high service time variability
Motivated by experience gained during the validation of a recent Approximate Mean Value Analysis (AMVA) model of modern shared memory architectures, this paper re-examines the &qu...
Derek L. Eager, Daniel J. Sorin, Mary K. Vernon
HPCA
2003
IEEE
15 years 10 months ago
Reconsidering Complex Branch Predictors
To sustain instruction throughput rates in more aggressively clocked microarchitectures, microarchitects have incorporated larger and more complex branch predictors into their des...
Daniel A. Jiménez