Sciweavers

421 search results - page 56 / 85
» Hardware efficient architectures for Eigenvalue computation
Sort
View
FPL
2007
Springer
99views Hardware» more  FPL 2007»
15 years 1 months ago
Disjoint Pattern Enumeration for Custom Instructions Identification
Extensible processors allow addition of application-specific custom instructions to the core instruction set architecture. These custom instructions are selected through an analys...
Pan Yu, Tulika Mitra
ICA3PP
2010
Springer
14 years 11 months ago
Function Units Sharing between Neighbor Cores in CMP
Abstract. Program behaviors reveal that programs have different sources requirement at different phases, even at continuous clocks. It is not a reasonable way to run different prog...
Tianzhou Chen, Jianliang Ma, Hui Yuan, Jingwei Liu...
FCCM
2005
IEEE
139views VLSI» more  FCCM 2005»
15 years 3 months ago
A Study of the Scalability of On-Chip Routing for Just-in-Time FPGA Compilation
Just-in-time (JIT) compilation has been used in many applications to enable standard software binaries to execute on different underlying processor architectures. We previously in...
Roman L. Lysecky, Frank Vahid, Sheldon X.-D. Tan
ICPP
2009
IEEE
15 years 4 months ago
Exploiting Simulation Slack to Improve Parallel Simulation Speed
Parallel simulation is a technique to accelerate microarchitecture simulation of CMPs by exploiting the inherent parallelism of CMPs. In this paper, we explore the simulation para...
Jianwei Chen, Murali Annavaram, Michel Dubois
DAC
2005
ACM
15 years 10 months ago
Power emulation: a new paradigm for power estimation
In this work, we propose a new paradigm called power emulation, which exploits hardware acceleration to drastically speedup power estimation. Power emulation is based on the obser...
Joel Coburn, Srivaths Ravi, Anand Raghunathan