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» Hardware interface design for real time embedded systems
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DDECS
2007
IEEE
201views Hardware» more  DDECS 2007»
15 years 4 months ago
Built in Defect Prognosis for Embedded Memories
: As scan compression replaces the traditional scan it is important to understand how it works with power. DFT MAX represents one of the two primary scan compression solutions used...
Prashant Dubey, Akhil Garg, Sravan Kumar Bhaskaran...
ICCD
2003
IEEE
123views Hardware» more  ICCD 2003»
15 years 7 months ago
Simplifying SoC design with the Customizable Control Processor Platform
With the circuit density available in today’s ASIC design systems, increased integration is possible creating more complexity in the design of a System on a Chip (SoC). IBM’s ...
C. Ross Ogilvie, Richard Ray, Robert Devins, Mark ...
MICRO
2003
IEEE
161views Hardware» more  MICRO 2003»
15 years 3 months ago
Design and Implementation of High-Performance Memory Systems for Future Packet Buffers
In this paper we address the design of a future high-speed router that supports line rates as high as OC-3072 (160 Gb/s), around one hundred ports and several service classes. Bui...
Jorge García-Vidal, Jesús Corbal, Ll...
TEI
2010
ACM
236views Hardware» more  TEI 2010»
15 years 4 months ago
StitchRV: multi-camera fiducial tracking
StitchRV is a fiducial and touch-tracking engine based on the popular reacTIVision fiducial tracking system. StitchRV combines video input from multiple cameras in real time, and ...
Sijie Wang, Allen Bevans, Alissa Nicole Antle
DATE
2003
IEEE
123views Hardware» more  DATE 2003»
15 years 3 months ago
RTOS Modeling for System Level Design
System level synthesis is widely seen as the solution for closing the productivity gap in system design. High level system models are used in system level design for early design ...
Andreas Gerstlauer, Haobo Yu, Daniel Gajski