1118 search results - page 163 / 224 » Hardware interface design for real time embedded systems |
FPL
2003
Springer
15 years 5 months ago
2003
Springer
This paper introduces the notion of a software decelerator, to be used in logic-centric system architectures. Functions are offloaded from logic to a processor, accepting a speed ...
111
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ISCA
2007
IEEE
15 years 6 months ago
2007
IEEE
Software cache-based side channel attacks are a serious new class of threats for computers. Unlike physical side channel attacks that mostly target embedded cryptographic devices,...
FDL
2005
IEEE
15 years 5 months ago
2005
IEEE
The support of heterogeneity at the specification level, that is, the ability to mix several models of computation (MoCs) in the system-level specification, is becoming increasing...
100
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DATE
2003
IEEE
15 years 5 months ago
2003
IEEE
Reduction of both the test suite size and the download time of test vectors is important in today's System-On-a-Chip designs. In this paper, a method for compressing the scan...
106
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EMSOFT
2004
Springer
15 years 5 months ago
2004
Springer
Basic retiming is an algorithm originally developed for hardware optimization. Software pipelining is a technique proposed to increase instruction-level parallelism for parallel p...