111 search results - page 22 / 23 » Hardware scheduling support in SMP architectures |
MICRO
2005
IEEE
13 years 12 months ago
2005
IEEE
An emerging trend in processor design is the addition of short vector instructions to general-purpose and embedded ISAs. Frequently, these extensions are employed using traditiona...
MICRO
2010
IEEE
13 years 4 months ago
2010
IEEE
SARC merges cache controller and network interface functions by relying on a single hardware primitive: each access checks the tag and the state of the addressed line for possible...
IPPS
2009
IEEE
14 years 29 days ago
2009
IEEE
Various studies have shown that OS jitter can degrade parallel program performance considerably at large processor counts. Most sources of system jitter fall broadly into 5 catego...
INFOCOM
2007
IEEE
14 years 19 days ago
2007
IEEE
Next-generation high-end Network Processors (NP) must address demands from both diversified applications and ever-increasing traffic pressure. One major challenge is to design an e...
PPOPP
2010
ACM
14 years 1 months ago
2010
ACM
To fully exploit multicore processors, applications are expected to provide a large degree of thread-level parallelism. While adequate for low core counts and their typical worklo...