397 search results - page 74 / 80 » Hardware software managed scratchpad memory for embedded sys... |
IEEEPACT
2006
IEEE
15 years 5 months ago
2006
IEEE
On machines with high-performance processors, the memory system continues to be a performance bottleneck. Compilers insert prefetch operations and reorder data accesses to improve...
112
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ASPLOS
2010
ACM
15 years 3 months ago
2010
ACM
Power consumption and DRAM latencies are serious concerns in modern chip-multiprocessor (CMP or multi-core) based compute systems. The management of the DRAM row buffer can signif...
SIGMETRICS
2008
ACM
14 years 11 months ago
2008
ACM
Enterprise customers are increasingly adopting MPLS (Multiprotocol Label Switching) VPN (Virtual Private Network) service that offers direct any-to-any reachability among the cust...
103
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LCTRTS
1998
Springer
15 years 3 months ago
1998
Springer
Abstract. Previously published methods for estimation of the worstcase execution time on contemporary processors with complex pipelines and multi-level memory hierarchies result in...
120
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LCTRTS
2010
Springer
14 years 9 months ago
2010
Springer
Chip multiprocessors (CMPs) are expected to be the building blocks for future computer systems. While architecting these emerging CMPs is a challenging problem on its own, program...