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ASPDAC
2004
ACM
120views Hardware» more  ASPDAC 2004»
15 years 5 months ago
Compiler based exploration of DSP energy savings by SIMD operations
— The growing use of digital signal processors (DSPs) in embedded systems necessitates the use of optimizing compilers supporting their special architecture features. Beside the ...
Markus Lorenz, Peter Marwedel, Thorsten Dräge...
ISCA
2010
IEEE
170views Hardware» more  ISCA 2010»
15 years 5 months ago
Relax: an architectural framework for software recovery of hardware faults
As technology scales ever further, device unreliability is creating excessive complexity for hardware to maintain the illusion of perfect operation. In this paper, we consider whe...
Marc de Kruijf, Shuou Nomura, Karthikeyan Sankaral...
ISCA
1996
IEEE
130views Hardware» more  ISCA 1996»
15 years 4 months ago
Informing Memory Operations: Providing Memory Performance Feedback in Modern Processors
Memory latency is an important bottleneck in system performance that cannot be adequately solved by hardware alone. Several promising software techniques have been shown to addres...
Mark Horowitz, Margaret Martonosi, Todd C. Mowry, ...
FCCM
2000
IEEE
122views VLSI» more  FCCM 2000»
15 years 4 months ago
Evaluating Hardware Compilation Techniques
Hardware compilation techniques which use highlevel programming languages to describe and synthesize hardware are gaining popularity. They are especially useful for reconfigurable...
Markus Weinhardt, Wayne Luk
RTCSA
2005
IEEE
15 years 5 months ago
Research Issues in the Development of Context-Aware Middleware Architectures
Context-aware middleware encompasses uniform ions and reliable services for common operations, supports for most of the tasks involved in dealing with context, and thus simplifyin...
Hung Quoc Ngo, Anjum Shehzad, Kim Anh Pham Ngoc, S...