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IISWC
2009
IEEE
15 years 6 months ago
Understanding PARSEC performance on contemporary CMPs
PARSEC is a reference application suite used in industry and academia to assess new Chip Multiprocessor (CMP) designs. No investigation to date has profiled PARSEC on real hardwa...
Major Bhadauria, Vincent M. Weaver, Sally A. McKee
HOTI
2005
IEEE
15 years 5 months ago
SIFT: Snort Intrusion Filter for TCP
Intrusion rule processing in reconfigurable hardware enables intrusion detection and prevention services to run at multi Gigabit/second rates. High-level intrusion rules mapped d...
Michael Attig, John W. Lockwood
DATE
2005
IEEE
104views Hardware» more  DATE 2005»
15 years 5 months ago
Queue Management in Network Processors
: - One of the main bottlenecks when designing a network processing system is very often its memory subsystem. This is mainly due to the state-of-the-art network links operating at...
Ioannis Papaefstathiou, Theofanis Orphanoudakis, G...
PPOPP
1993
ACM
15 years 3 months ago
Integrating Message-Passing and Shared-Memory: Early Experience
This paper discusses some of the issues involved in implementing a shared-address space programming model on large-scale, distributed-memory multiprocessors. While such a programm...
David A. Kranz, Kirk L. Johnson, Anant Agarwal, Jo...
ASPLOS
1987
ACM
15 years 3 months ago
Machine-Independent Virtual Memory Management for Paged Uniprocessor and Multiprocessor Architectures
This paper describes the design and implementation of virtual memory management within the CMU Mach Operating System and the experiences gained by the Mach kernel group in porting...
Richard F. Rashid, Avadis Tevanian, Michael Young,...