115 search results - page 18 / 23 » Hardware synthesis from protocol specifications in LOTOS |
DATE
2010
IEEE
15 years 1 months ago
2010
IEEE
─ Error tolerance formally captures the notion that – for a wide variety of applications including audio, video, graphics, and wireless communications – a defective chip that...
FPL
2005
Springer
15 years 3 months ago
2005
Springer
The paper analyses and compares alternative iterative and recursive implementations of FPGA circuits for various problems. Two types of recursive calls have been examined, namely ...
FPGA
2004
ACM
15 years 2 months ago
2004
ACM
The cost functions used to evaluate logic synthesis transformations for FPGAs are far removed from the final speed and routability determined after placement, routing and timing a...
ICCAD
2007
IEEE
15 years 1 months ago
2007
IEEE
Stepwise refinement is at the core of many approaches to synthesis and optimization of hardware and software systems. For instance, it can be used to build a synthesis approach for...
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INTEGRATION
2008
14 years 9 months ago
2008
With the growing complexity in consumer embedded products, new tendencies forecast heterogeneous Multi-Processor SystemsOn-Chip (MPSoCs) consisting of complex integrated component...