In traditional distributed embedded system designs, control information is often replicated across several processes and kept coherent by application-specific mechanisms. Conseque...
Pai H. Chou, Ken Hines, Kurt Partridge, Gaetano Bo...
Register Transfer Level (RTL) synthesis model which simplified the design of clocked circuits allowed design automation boost and VLSI progress for more than a decade. Shrinking t...
Alexander B. Smirnov, Alexander Taubin, Ming Su, M...
This reported work applies a transformational synthesis approach to hardware/software codesign. In this approach, the process of algorithm design is coupled early on with hardware...
Tommy King-Yin Cheung, Graham R. Hellestrand, Pras...
This paper presents a new pairing protocol that allows two CPU-constrained wireless devices Alice and Bob to establish a shared secret at a very low cost. To our knowledge, this i...
Balanced dynamic dual-rail gates and asynchronous circuits have been shown, if implemented correctly, to have natural and efficient resistance to side-channel attacks. Despite thei...
Konrad J. Kulikowski, Alexander B. Smirnov, Alexan...