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FPL
1998
Springer
82views Hardware» more  FPL 1998»
15 years 8 months ago
Pebble: A Language for Parametrised and Reconfigurable Hardware Design
Abstract. Pebble is a simple language designed to improve the productivity and effectiveness of hardware design. It improves productivity by adopting reusable word-level and bit-le...
Wayne Luk, Steve McKeever
HPCA
1996
IEEE
15 years 8 months ago
Co-Scheduling Hardware and Software Pipelines
Exploiting instruction-level parallelism (ILP) is extremely important for achieving high performance in application specific instruction set processors (ASIPs) and embedded process...
Ramaswamy Govindarajan, Erik R. Altman, Guang R. G...
ICCD
1993
IEEE
111views Hardware» more  ICCD 1993»
15 years 8 months ago
Ravel-XL: A Hardware Accelerator for Assigned-Delay Compiled-Code Logic Gate Simulation
Ravel-XL is a single-boardhardware accelerator for gate-level digital logic simulation. It uses a standard levelizedcode approach to statically schedule gate evaluations.However, u...
Michael A. Riepe, João P. Marques Silva, Ka...
ICPP
1994
IEEE
15 years 8 months ago
An Integrated Hardware/Software Data Prefetching Scheme for Shared-Memory Multiprocessors
Both hardware and software prefetching have been shown to be e ective in tolerating the large memory latencies inherent in shared-memory multiprocessors however, both types of pre...
Edward H. Gornish, Alexander V. Veidenbaum
ASPDAC
2007
ACM
98views Hardware» more  ASPDAC 2007»
15 years 8 months ago
Efficient Automata-Based Assertion-Checker Synthesis of SEREs for Hardware Emulation
In this paper, we present a method for generating checker circuits from sequential-extended regular expressions (SEREs). Such sequences form the core of increasingly-used Assertion...
Marc Boule, Zeljko Zilic