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GLVLSI
2002
IEEE
127views VLSI» more  GLVLSI 2002»
15 years 9 months ago
A new look at hardware maze routing
This paper describes a new design for a hardware accelerator to support grid-based Maze Routing. Based on the direct mapped approach of Breuer and Shamsa [3], this work refines th...
John A. Nestor
CHES
2001
Springer
191views Cryptology» more  CHES 2001»
15 years 9 months ago
A Scalable GF(p) Elliptic Curve Processor Architecture for Programmable Hardware
Abstract. This work proposes a new elliptic curve processor architecture for the computation of point multiplication for curves defined over fields GF(p). This is a scalable arch...
Gerardo Orlando, Christof Paar
TACAS
2001
Springer
160views Algorithms» more  TACAS 2001»
15 years 9 months ago
Hardware/Software Co-Design Using Functional Languages
In previous work we have developed and prototyped a silicon compiler which translates a functional language (SAFL) into hardware. Here we present a SAFL-level program transformati...
Alan Mycroft, Richard Sharp
DAC
1999
ACM
15 years 8 months ago
Hardware Reuse at the Behavioral Level
Standard interfaces for hardware reuse are currently de ned at the structural level. In contrast to this, our contribution de nes the reuse interface at the behavioral registertra...
Patrick Schaumont, Radim Cmar, Serge Vernalde, Mar...
ISSS
1998
IEEE
107views Hardware» more  ISSS 1998»
15 years 8 months ago
Integrating Communication Protocol Selection with Partitioning in Hardware/Software Codesign
This paper presents a codesign approach which incorporates communication protocol selection as a design parameter within hardware/software partitioning. The presented approach tak...
Peter Voigt Knudsen, Jan Madsen