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DATE
2006
IEEE
113views Hardware» more  DATE 2006»
15 years 10 months ago
An interprocedural code optimization technique for network processors using hardware multi-threading support
Sophisticated C compiler support for network processors (NPUs) is required to improve their usability and consequently, their acceptance in system design. Nonetheless, high-level ...
Hanno Scharwächter, Manuel Hohenauer, Rainer ...
HICSS
2006
IEEE
131views Biometrics» more  HICSS 2006»
15 years 10 months ago
Design and Characterization of a Hardware Encryption Management Unit for Secure Computing Platforms
— Software protection is increasingly necessary for uses in commercial systems, digital content distributors, and military systems. The Secure Software (SecSoft) architecture is ...
Anthony J. Mahar, Peter M. Athanas, Stephen D. Cra...
ISCAS
2006
IEEE
108views Hardware» more  ISCAS 2006»
15 years 10 months ago
A low complexity hardware architecture for motion estimation
This paper tackles the problem of accelerating The rest of this paper is organised as follows: section II motion estimation for video processing. A novel architecture details relat...
Daniel Larkin, Vlenti. Muresan, Noel E. O'Connor
SMI
2006
IEEE
209views Image Analysis» more  SMI 2006»
15 years 10 months ago
Hardware Rendering of 3D Geometry with Elevation Maps
We present a generic framework for realtime rendering of 3D surfaces. We use the common elevation map primitive, by which a given surface is decomposed into a set of patches. Each...
Tilo Ochotta, Stefan Hiller
DFT
2005
IEEE
109views VLSI» more  DFT 2005»
15 years 10 months ago
Hardware Testing For Error Tolerant Multimedia Compression based on Linear Transforms
In this paper, we propose a system-level error tolerance scheme for systems where a linear transform is combined with quantization. These are key components in multimedia compress...
In Suk Chong, Antonio Ortega