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CODES
2004
IEEE
15 years 8 months ago
Facilitating reuse in hardware models with enhanced type inference
High-level hardware modeling is an essential, yet time-consuming, part of system design. However, effective component-based reuse in hardware modeling languages can reduce model c...
Manish Vachharajani, Neil Vachharajani, Sharad Mal...
109
Voted
CSB
2004
IEEE
123views Bioinformatics» more  CSB 2004»
15 years 8 months ago
A New Hardware Architecture for Genomic and Proteomic Sequence Alignment
We describe a novel hardware architecture for genomic and proteomic sequence alignment which achieves a speed-up of two to three orders of magnitude over Smith-Waterman dynamic pr...
Greg Knowles, Paul Gardner-Stephen
147
Voted
CHES
2006
Springer
179views Cryptology» more  CHES 2006»
15 years 8 months ago
Offline Hardware/Software Authentication for Reconfigurable Platforms
Abstract. Many Field-Programmable Gate Array (FPGA) based systems utilize third-party intellectual property (IP) in their development. When they are deployed in non-networked envir...
Eric Simpson, Patrick Schaumont
EH
2004
IEEE
105views Hardware» more  EH 2004»
15 years 8 months ago
Robust Sensor Systems using Evolvable Hardware
This paper describes a system that is robust with respect to sensor failure. The system utilizes multiple sensor inputs (three in this case) connected to a programmable device (FP...
James Hereford, Charles Pruitt
167
Voted
DSD
2006
IEEE
135views Hardware» more  DSD 2006»
15 years 8 months ago
Hardware-Software Codesign of a Vector Co-processor for Public Key Cryptography
Until now, most cryptography implementations on parallel architectures have focused on adapting the software to SIMD architectures initially meant for media applications. In this ...
Jacques J. A. Fournier, Simon W. Moore