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130
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ICCD
2002
IEEE
122views Hardware» more  ICCD 2002»
15 years 10 months ago
Cost-Effective Concurrent Test Hardware Design for Linear Analog Circuits
Concurrent detection of failures in analog circuits is becoming increasingly more important as safety-critical systems become more widespread. A methodology for the automatic desi...
Sule Ozev, Alex Orailoglu
ISWC
2002
IEEE
15 years 9 months ago
Micro-Accelerometer Based Hardware Interfaces for Wearable Computer Mixed Reality Applications
Human interaction with wearable computers is an important research issue, especially when combined with mixed reality (MR) applications. Natural and non-obtrusive means of interac...
Adrian David Cheok, Krishnamoorthy Ganesh Kumar, S...
142
Voted
FCCM
2000
IEEE
103views VLSI» more  FCCM 2000»
15 years 9 months ago
A Networked FPGA-Based Hardware Implementation of a Neural Network Application
This paper describes a networked FPGA-based implementation of the FAST (Flexible Adaptable-Size Topology) architecture, a Arti cial Neural Network (ANN) that dynamically adapts it...
Héctor Fabio Restrepo, Ralph Hoffmann, Andr...
122
Voted
SC
2000
ACM
15 years 9 months ago
Using Hardware Performance Monitors to Isolate Memory Bottlenecks
In this paper, we present and evaluate two techniques that use different styles of hardware support to provide data structure specific processor cache information. In one approach...
Bryan R. Buck, Jeffrey K. Hollingsworth
FPL
1999
Springer
103views Hardware» more  FPL 1999»
15 years 9 months ago
IP Validation for FPGAs Using Hardware Object Technology
Although verification and simulation tools are always improving, the results they provide remain hard to analyze and interpret. On one hand, verification sticks to the functional ...
Steve Casselman, John Schewel, Christophe Beaumont