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117
Voted
EH
2003
IEEE
97views Hardware» more  EH 2003»
15 years 10 months ago
Evolution of Combinatonial and Sequential On-Line Self-Diagnosing Hardware
The evolution of circuits with on-line built-in self-test is attempted in simulation for a full adder, a two bit multiplier and an edge triggered D-Latch. Results show that evolve...
Miguel Garvie, Adrian Thompson
FCCM
2003
IEEE
148views VLSI» more  FCCM 2003»
15 years 10 months ago
A Hardware Gaussian Noise Generator for Channel Code Evaluation
Hardware simulation of channel codes offers the potential of improving code evaluation speed by orders of magnitude over workstation- or PC-based simulation. We describe a hardwar...
Dong-U Lee, Wayne Luk, John D. Villasenor, Peter Y...
143
Voted
MICRO
2003
IEEE
96views Hardware» more  MICRO 2003»
15 years 10 months ago
Scalable Hardware Memory Disambiguation for High ILP Processors
This paper describes several methods for improving the scalability of memory disambiguation hardware for future high ILP processors. As the number of in-flight instructions grows...
Simha Sethumadhavan, Rajagopalan Desikan, Doug Bur...
112
Voted
DATE
2010
IEEE
107views Hardware» more  DATE 2010»
15 years 10 months ago
An error-correcting unordered code and hardware support for robust asynchronous global communication
A new delay-insensitive data encoding scheme for global asynchronous communication is introduced. The goal of this work is to combine the timing-robustness of delay-insensitive (i....
Melinda Y. Agyekum, Steven M. Nowick
149
Voted
SIGGRAPH
1999
ACM
15 years 9 months ago
Realistic, Hardware-Accelerated Shading and Lighting
With fast 3D graphics becoming more and more available even on low end platforms, the focus in hardware-accelerated rendering is beginning to shift towards higher quality renderin...
Wolfgang Heidrich, Hans-Peter Seidel