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VEE
2012
ACM
187views Virtualization» more  VEE 2012»
14 years 17 days ago
DDGacc: boosting dynamic DDG-based binary optimizations through specialized hardware support
Dynamic Binary Translators (DBT) and Dynamic Binary Optimization (DBO) by software are used widely for several reasons including performance, design simplification and virtualiza...
Demos Pavlou, Enric Gibert, Fernando Latorre, Anto...
CVPR
2003
IEEE
16 years 7 months ago
Multi-Resolution Real-Time Stereo on Commodity Graphics Hardware
In this paper a stereo algorithm suitable for implementation on commodity graphics hardware is presented. This is important since it allows to free up the main processor for other...
Ruigang Yang, Marc Pollefeys
VIS
2005
IEEE
128views Visualization» more  VIS 2005»
16 years 6 months ago
Hardware-Accelerated Simulated Radiography
We present the application of hardware accelerated volume rendering algorithms to the simulation of radiographs as an aid to scientists designing experiments, validating simulatio...
Cláudio T. Silva, Daniel E. Laney, Nelson L...
DAC
2000
ACM
16 years 6 months ago
Hardware implementation of communication protocols modeled by concurrent EFSMs with multi-way synchronization
In this paper, we propose a technique to implement communication protocols as hardware circuits using a model of concurrent EFSMs with multi-way synchronization. Since use of mult...
Hisaaki Katagiri, Keiichi Yasumoto, Akira Kitajima...
CHES
2009
Springer
162views Cryptology» more  CHES 2009»
16 years 5 months ago
Hardware Accelerator for the Tate Pairing in Characteristic Three Based on Karatsuba-Ofman Multipliers
Abstract. This paper is devoted to the design of fast parallel accelerators for the cryptographic Tate pairing in characteristic three over supersingular elliptic curves. We propos...
Jean-Luc Beuchat, Jérémie Detrey, Ni...