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DT
2006
113views more  DT 2006»
15 years 4 months ago
The Challenges of Synthesizing Hardware from C-Like Languages
at their abstractions are similar to data types and operations supplied by conventional processors. A core principle of BCPL is its memory model: an The Challenges of Synthesizing ...
Stephen A. Edwards
137
Voted
ENTCS
2006
136views more  ENTCS 2006»
15 years 4 months ago
A "Hardware Compiler" Semantics for Handel-C
We present a denotational semantics for the hardware compilation language Handel-C that maps language constructs to a set of equations, which describe the structure of the resulti...
Andrew Butterfield, Jim Woodcock
JSA
2007
142views more  JSA 2007»
15 years 3 months ago
Efficient FPGA hardware development: A multi-language approach
This paper presents a multi-language framework to FPGA hardware development which aims to satisfy the dual requirement of high level hardware design and efficient hardware impleme...
Khaled Benkrid, Abdsamad Benkrid, S. Belkacemi
137
Voted
DSD
2009
IEEE
147views Hardware» more  DSD 2009»
15 years 7 months ago
A High Performance Hardware Architecture for One Bit Transform Based Motion Estimation
Motion Estimation (ME) is the most computationally intensive part of video compression and video enhancement systems. One bit transform (1BT) based ME algorithms have low computat...
Abdulkadir Akin, Yigit Dogan, Ilker Hamzaoglu
92
Voted
ASAP
2007
IEEE
123views Hardware» more  ASAP 2007»
15 years 10 months ago
A memcpy Hardware Accelerator Solution for Non Cache-line Aligned Copies
In this paper, we present a hardware solution to perform non cache-line aligned memory copies allowing the commonly used memcpy function to cope with word copies. The main purpose...
Filipa Duarte, Stephan Wong