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177
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DSD
2011
IEEE
14 years 3 months ago
2011
IEEE
Abstract—We present a new low-level interfacing scheme for connecting custom accelerators to processors that tolerates latencies that usually occur when accessing hardware accele...
147
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ARC
2009
Springer
15 years 10 months ago
2009
Springer
Spiking Neural Networks (SNNs) model the biological functions of the human brain enabling neuro/computer scientists to investigate how arrays of neurons can be used to solve comput...
159
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JTRES
2009
ACM
15 years 10 months ago
2009
ACM
This paper describes hardware methods, a lightweight and platform-independent scheme for linking real-time Java code to co-processors implemented using a hardware description lang...
121
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FPL
2007
Springer
15 years 10 months ago
2007
Springer
This paper describes an execution cache that uses process migration between hardware and software contexts by way of run-time reconfiguration (RTR) of Field Programmable Gate Arr...
124
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DATE
2006
IEEE
15 years 10 months ago
2006
IEEE
The allocation of device variables on I/O registers affects the code size and performance of an I/O device driver. This work seeks the allocation with the minimal software or hard...