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FCCM
1999
IEEE
127views VLSI» more  FCCM 1999»
15 years 8 months ago
Mapping of an Automated Target Recognition Application from a Graphical Software Environment to FPGA-Based Reconfigurable Hardwa
A significant obstacle to the widespread adoption of FPGAbased configurable computing hardware has been the difficulty of mapping applications onto this hardware. We are developin...
Benjamin A. Levine, Senthil Natarajan, Chandra Tan...
ARCS
1997
Springer
15 years 8 months ago
A Novel Universal Sequencer Hardware
This paper introduces a powerful novel sequencer hardware for controlling computational machines and for structured DMA (direct memory access) applications. The paper introduces t...
Reiner W. Hartenstein, Jürgen Becker, Michael...
ASPDAC
2006
ACM
109views Hardware» more  ASPDAC 2006»
15 years 7 months ago
Hardware debugging method based on signal transitions and transactions
- This paper proposes a hardware design debugging method, Transition and Transaction Tracer (TTT), which probes and records the signals of interest for a long time, hours, days, or...
Nobuyuki Ohba, Kohji Takano
ACIVS
2008
Springer
15 years 6 months ago
An Efficient Hardware Architecture without Line Memories for Morphological Image Processing
In this paper, we present a novel hardware architecture to achieve erosion and dilation with a large structuring element. We are proposing a modification of HGW algorithm with a bl...
Christophe Clienti, Michel Bilodeau, Serge Beucher
AAAI
2006
15 years 5 months ago
Constraint-Based Random Stimuli Generation for Hardware Verification
We report on random stimuli generation for hardware verification in IBM as a major application of various artificial intelligence technologies, including knowledge representation,...
Yehuda Naveh, Michal Rimon, Itai Jaeger, Yoav Katz...