A significant obstacle to the widespread adoption of FPGAbased configurable computing hardware has been the difficulty of mapping applications onto this hardware. We are developin...
Benjamin A. Levine, Senthil Natarajan, Chandra Tan...
This paper introduces a powerful novel sequencer hardware for controlling computational machines and for structured DMA (direct memory access) applications. The paper introduces t...
- This paper proposes a hardware design debugging method, Transition and Transaction Tracer (TTT), which probes and records the signals of interest for a long time, hours, days, or...
In this paper, we present a novel hardware architecture to achieve erosion and dilation with a large structuring element. We are proposing a modification of HGW algorithm with a bl...
Christophe Clienti, Michel Bilodeau, Serge Beucher
We report on random stimuli generation for hardware verification in IBM as a major application of various artificial intelligence technologies, including knowledge representation,...
Yehuda Naveh, Michal Rimon, Itai Jaeger, Yoav Katz...