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ISQED
2005
IEEE
125views Hardware» more  ISQED 2005»
15 years 5 months ago
A New Method for Design of Robust Digital Circuits
As technology continues to scale beyond 100nm, there is a significant increase in performance uncertainty of CMOS logic due to process and environmental variations. Traditional c...
Dinesh Patil, Sunghee Yun, Seung-Jean Kim, Alvin C...
ASPDAC
2005
ACM
140views Hardware» more  ASPDAC 2005»
15 years 5 months ago
A multi-level transmission line network approach for multi-giga hertz clock distribution
-In high performance systems, process variations and fluctuations of operating environments have significant impact on the clock skew. Recently, hybrid structures of H-tree and m...
Hongyu Chen, Chung-Kuan Cheng
ISLPED
2005
ACM
111views Hardware» more  ISLPED 2005»
15 years 5 months ago
Peak temperature control and leakage reduction during binding in high level synthesis
Temperature is becoming a first rate design criterion in ASICs due to its negative impact on leakage power, reliability, performance, and packaging cost. Incorporating awareness o...
Rajarshi Mukherjee, Seda Ogrenci Memik, Gokhan Mem...
HICSS
2003
IEEE
127views Biometrics» more  HICSS 2003»
15 years 5 months ago
Testing Design of a Social Innovation The Environmental Mitigation Banking System
This paper attempts to evaluate the performance of an environmental mitigation banking system operating under different regulatory. Pricing and subsidization policies using system...
Khalid Saeed, Atsushi Fukuda
ICCAD
2000
IEEE
124views Hardware» more  ICCAD 2000»
15 years 4 months ago
A Methodology for Verifying Memory Access Protocols in Behavioral Synthesis
— Memory is one of the most important components to be optimized in the several phases of the synthesis process. ioral synthesis, a memory is viewed as an abstract construct whic...
Gernot Koch, Taewhan Kim, Reiner Genevriere