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FPGA
2008
ACM
145views FPGA» more  FPGA 2008»
15 years 3 months ago
FPGA interconnect design using logical effort
Logical effort (LE) is a linear technique for modelling the delay of a circuit in a technology independent manner. It offers the potential to simplify delay models for FPGAs and g...
Haile Yu, Yuk Hei Chan, Philip Heng Wai Leong
GLOBECOM
2008
IEEE
15 years 8 months ago
Performance Metric Sensitivity Computation for Optimization and Trade-Off Analysis in Wireless Networks
Abstract—We develop and evaluate a new method for estimating and optimizing various performance metrics for multihop wireless networks, including MANETs. We introduce an approxim...
John S. Baras, Vahid Tabatabaee, George Papageorgi...
QEST
2006
IEEE
15 years 7 months ago
Optimization of Cache Expiration Dates in Content Networks
One of the fundamental decisions in content networks is how the information about the existing contents is deployed and accessed. In particular, in many content network architectu...
Héctor Cancela, Pablo Rodríguez-Bocc...
WSC
2007
15 years 3 months ago
IFAO-SIMO: a spatial-simulation based facility network optimization framework
This paper describes an innovative framework, iFAOSimo, which integrates optimization, simulation and GIS (geographic information system) techniques to handle complex spatial faci...
Ming Xie, Wei Wang, Wen Jun Yin, Jin Dong
INFOCOM
2011
IEEE
14 years 5 months ago
Feasibility and optimization of delay guarantees for non-homogeneous flows in IEEE 802.11 WLANs
—Due to the rapid growth of real-time applications and the ubiquity of IEEE 802.11 MAC as a layer-2 protocol for wireless local area networks (WLANs), it is of increasing interes...
Yan Gao, Chee Wei Tan, Ying Huang, Zheng Zeng, P. ...