Test application time is an important factor in the overall cost of VLSI chip testing. We present a new ATPG approach for generating compact test sequences for sequential circuits...
Yanti Santoso, Matthew C. Merten, Elizabeth M. Rud...
A method is presented for identifying primitive path-delay faults in non-scan sequential circuits and generating robust tests for all robustly testable primitive faults. It uses t...
In this paper, we present a simple method for generating random-based signatures when random number generators are either unavailable or of suspected quality (malicious or accident...
We present an approach for the generation of components for a software renovation factory. These components are generated from a context-free grammar definition that recognizes t...
Mark van den Brand, M. P. A. Sellink, Chris Verhoe...
This paper presents a novel approach for automatic test pattern generation of asynchronous circuits. The techniques used for this purpose assume that the circuit can only be exerc...