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DATE
1999
IEEE
120views Hardware» more  DATE 1999»
15 years 2 months ago
FreezeFrame: Compact Test Generation Using a Frozen Clock Strategy
Test application time is an important factor in the overall cost of VLSI chip testing. We present a new ATPG approach for generating compact test sequences for sequential circuits...
Yanti Santoso, Matthew C. Merten, Elizabeth M. Rud...
ICCAD
1998
IEEE
116views Hardware» more  ICCAD 1998»
15 years 2 months ago
On primitive fault test generation in non-scan sequential circuits
A method is presented for identifying primitive path-delay faults in non-scan sequential circuits and generating robust tests for all robustly testable primitive faults. It uses t...
Ramesh C. Tekumalla, Premachandran R. Menon
SACRYPT
1998
Springer
15 years 2 months ago
Computational Alternatives to Random Number Generators
In this paper, we present a simple method for generating random-based signatures when random number generators are either unavailable or of suspected quality (malicious or accident...
David M'Raïhi, David Naccache, David Pointche...
WCRE
1997
IEEE
15 years 2 months ago
Generation of Components for Software Renovation Factories from Context-Free Grammars
We present an approach for the generation of components for a software renovation factory. These components are generated from a context-free grammar definition that recognizes t...
Mark van den Brand, M. P. A. Sellink, Chris Verhoe...
DAC
1997
ACM
15 years 2 months ago
Automatic Generation of Synchronous Test Patterns for Asynchronous Circuits
This paper presents a novel approach for automatic test pattern generation of asynchronous circuits. The techniques used for this purpose assume that the circuit can only be exerc...
Oriol Roig, Jordi Cortadella, Marco A. Peña...