Sciweavers

11097 search results - page 1960 / 2220
» Hera presentation generator
Sort
View
120
Voted
IEEEPACT
2006
IEEE
15 years 6 months ago
Fast, automatic, procedure-level performance tuning
This paper presents an automated performance tuning solution, which partitions a program into a number of tuning sections and finds the best combination of compiler options for e...
Zhelong Pan, Rudolf Eigenmann
105
Voted
IPPS
2006
IEEE
15 years 6 months ago
GPU-ABiSort: optimal parallel sorting on stream architectures
In this paper, we present a novel approach for parallel sorting on stream processing architectures. It is based on adaptive bitonic sorting. For sorting n values utilizing p strea...
Alexander Greß, Gabriel Zachmann
ISCAS
2006
IEEE
133views Hardware» more  ISCAS 2006»
15 years 6 months ago
Neuronal ion-channel dynamics in silicon
Abstract— We present a simple silicon circuit for modelling voltagedependent ion channels found within neural cells, capturing both the gating particle’s sigmoidal activation (...
Kai M. Hynna, Kwabena Boahen
ISCAS
2006
IEEE
112views Hardware» more  ISCAS 2006»
15 years 6 months ago
Silicon neurons that inhibit to synchronize
Abstract—We present a silicon neuron that uses shunting inhibition (conductance-based) with a synaptic rise-time to achieve synchrony. Synaptic rise-time promotes synchrony by de...
John V. Arthur, Kwabena Boahen
RTCSA
2006
IEEE
15 years 6 months ago
Integrating Compiler and System Toolkit Flow for Embedded VLIW DSP Processors
To support high-performance and low-power for multimedia applications and for hand-held devices, embedded VLIW DSP processors are of research focus. With the tight resource constr...
Chi Wu, Kun-Yuan Hsieh, Yung-Chia Lin, Chung-Ju Wu...
« Prev « First page 1960 / 2220 Last » Next »