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ISCA
2010
IEEE
232views Hardware» more  ISCA 2010»
15 years 4 months ago
Data marshaling for multi-core architectures
Previous research has shown that Staged Execution (SE), i.e., dividing a program into segments and executing each segment at the core that has the data and/or functionality to bes...
M. Aater Suleman, Onur Mutlu, José A. Joao,...
ERSA
2007
177views Hardware» more  ERSA 2007»
15 years 1 months ago
Energy-Aware System Synthesis for Reconfigurable Chip Multiprocessors
- Even though state-of-the-art FPGAs present new opportunities in exploring low-cost high-performance architectures for floating-point scientific applications, they also pose serio...
Xiaofang Wang, Sotirios G. Ziavras, Jie Hu
ATAL
2010
Springer
15 years 20 days ago
Finding approximate competitive equilibria: efficient and fair course allocation
In the course allocation problem, a university administrator seeks to efficiently and fairly allocate schedules of over-demanded courses to students with heterogeneous preferences...
Abraham Othman, Tuomas Sandholm, Eric Budish
CUZA
2002
129views more  CUZA 2002»
14 years 11 months ago
Ad Hoc Metacomputing with Compeer
Metacomputing allows the exploitation of geographically seperate, heterogenous networks and resources. Most metacomputers are feature rich and carry a long, complicated installati...
Keith Power, John P. Morrison
ANCS
2007
ACM
15 years 3 months ago
Ruler: high-speed packet matching and rewriting on NPUs
Programming specialized network processors (NPU) is inherently difficult. Unlike mainstream processors where architectural features such as out-of-order execution and caches hide ...
Tomas Hruby, Kees van Reeuwijk, Herbert Bos