165 search results - page 27 / 33 » Heterogeneous systems on chip and systems in package |
ASAP
2008
IEEE
15 years 4 months ago
2008
IEEE
As semiconductor processing technology continues to scale down, managing reliability becomes an increasingly difficult challenge in high-performance microprocessor design. Transie...
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HIPC
2004
Springer
15 years 3 months ago
2004
Springer
Parasitic extraction techniques are used to estimate signal delay in VLSI chips. Inductance extraction is a critical component of the parasitic extraction process in which on-chip ...
ISQED
2003
IEEE
15 years 2 months ago
2003
IEEE
—As the operating frequency of digital systems increases and voltage swing decreases, it becomes very important to characterize and analyze power distribution networks (PDNs) acc...
CODES
2005
IEEE
15 years 3 months ago
2005
IEEE
In order to meet flexibility, performance and energy efficiency constraints, future SoC (System-on-Chip) designs will contain an increasing number of heterogeneous processor cor...
DATE
2004
IEEE
15 years 1 months ago
2004
IEEE
Future Systems-on-Chips will include multiple heterogeneous processing units, with complex data-dependent shared resource access patterns dictating the performance of a design. Cu...