41 search results - page 3 / 9 » Heuristic approach to optimize the number of test cases for ... |
VTS
1996
IEEE
13 years 10 months ago
1996
IEEE
In this paper we investigate optimal voltage testing approaches for physically-based faults in CMOS circuits. We describe the general nature of the problem and then focus on two f...
ISQED
2007
IEEE
14 years 16 days ago
2007
IEEE
In nanometer regime, the effects of variations are having an increasing impact on the delay and power characteristics of devices as well as the yield of the circuit. Statistical t...
DAC
2004
ACM
14 years 7 months ago
2004
ACM
As across-chip interconnect delays can exceed a clock cycle, wire pipelining becomes essential in high performance designs. Although it allows higher clock frequencies, it may cha...
GECCO
2009
Springer
14 years 25 days ago
2009
Springer
Following a number of recent papers investigating the possibility of optimal comparison-based optimization algorithms for a given distribution of probability on fitness functions...
CORR
2010
Springer
13 years 3 months ago
2010
Springer
In this paper we study the partitioning approach for multiprocessor real-time scheduling. This approach seems to be the easiest since, once the partitioning of the task set has be...