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ICCAD
2002
IEEE
92views Hardware» more  ICCAD 2002»
15 years 8 months ago
ECO algorithms for removing overlaps between power rails and signal wires
Design ECO commonly happens in industry due to constraints or target changes from manufacturing, marketing, reliability, or performance. At each step, designers usually want to mo...
Hua Xiang, Kai-Yuan Chao, D. F. Wong
ISQED
2005
IEEE
81views Hardware» more  ISQED 2005»
15 years 5 months ago
Exact Algorithms for Coupling Capacitance Minimization by Adding One Metal Layer
Due to the rapid development of manufacturing process technology and tight marketing schedule, the chip design and manufacturing always work toward an integrated solution to achie...
Hua Xiang, Kai-Yuan Chao, Martin D. F. Wong
BMAS
2000
IEEE
15 years 4 months ago
Verilog-AMS: Mixed-Signal Simulation and Cross Domain Connect Modules
Verilog-AMS is one of the major mixed-signal hardware description languages on today’s market. In addition to the extended capabilities to model analog and digital behavior, the...
Peter Frey, Donald O'Riordan
ICDE
2006
IEEE
222views Database» more  ICDE 2006»
16 years 1 months ago
CLAN: An Algorithm for Mining Closed Cliques from Large Dense Graph Databases
Most previously proposed frequent graph mining algorithms are intended to find the complete set of all frequent, closed subgraphs. However, in many cases only a subset of the freq...
Jianyong Wang, Zhiping Zeng, Lizhu Zhou
ICDE
2004
IEEE
151views Database» more  ICDE 2004»
16 years 1 months ago
Benchmarking SAP R/3 Archiving Scenarios
According to a survey of the University of Berkeley [6], about 5 Exabytes of new information has been created in 2002. This information explosion affects also the database volumes...
Bernhard Zeller, Alfons Kemper