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DAC
2000
ACM
16 years 22 days ago
Unifying behavioral synthesis and physical design
eously demand shorter and less costly design cycles. Designing at higher levels of abstraction makes both objectives achievable, but enabling techniques like behavioral synthesis h...
William E. Dougherty, Donald E. Thomas
VLSID
2002
IEEE
159views VLSI» more  VLSID 2002»
16 years 4 days ago
Challenges in the Design of a Scalable Data-Acquisition and Processing System-on-Silicon
Increasing complexity of the functionalities and the resultant growth in number of gates integrated in a chip coupled with shrinking geometries and short cycle time requirements br...
Karanth Shankaranarayana, Soujanna Sarkar, R. Venk...
LCTRTS
2010
Springer
15 years 6 months ago
Design exploration and automatic generation of MPSoC platform TLMs from Kahn Process Network applications
With increasingly more complex Multi-Processor Systems on Chip (MPSoC) and shortening time-to- market projections, Transaction Level Modeling and Platform Aware Design are seen as...
Ines Viskic, Lochi Lo Chi Yu Lo, Daniel Gajski
MEMOCODE
2007
IEEE
15 years 6 months ago
MEMOCODE 2007 Co-Design Contest
New to the 2007 MEMOCODE conference is the HW/SW Co-Design Contest. Members of the technical and steering committees from MEMOCODE 2006 thought that the co-design practice is dist...
Forrest Brewer, James C. Hoe
FPGA
2005
ACM
215views FPGA» more  FPGA 2005»
15 years 5 months ago
Design, layout and verification of an FPGA using automated tools
Creating a new FPGA is a challenging undertaking because of the significant effort that must be spent on circuit design, layout and verification. It currently takes approximately ...
Ian Kuon, Aaron Egier, Jonathan Rose