64 search results - page 10 / 13 » Hierarchical Optimization of Asynchronous Circuits |
112
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CF
2004
ACM
15 years 7 months ago
2004
ACM
Nanoelectronics research has primarily focused on devices. By contrast, not much has been published on innovations at higher layers: we know little about how to construct circuits...
118
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ICCAD
2004
IEEE
15 years 10 months ago
2004
IEEE
—In this paper, we present a new block budgeting algorithm which speeds up timing closure in timing driven hierarchical flows. After a brief description of the addressed flow, ...
102
Voted
ISPD
2004
ACM
15 years 7 months ago
2004
ACM
This paper presents an efficient method for optimizing the design of power/ground (P/G) networks by using locally regular, globally irregular grids. The procedure divides the pow...
109
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ICCAD
2005
IEEE
15 years 10 months ago
2005
IEEE
In this paper we propose a novel analog design optimization methodology to address two key aspects of top-down system-level design: (1) how to optimally compare and select analog ...
147
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NOCS
2008
IEEE
15 years 8 months ago
2008
IEEE
In this paper we examine a latency insensitive network composed of very fast and simple circuits that connects SoC cores that are also latency insensitive, de-synchronized, or asy...