64 search results - page 9 / 13 » Hierarchical Optimization of Asynchronous Circuits |
90
Voted
ICCAD
1999
IEEE
15 years 1 months ago
1999
IEEE
Identifying repeating structural regularities in circuits allows the minimization of synthesis, optimization, and layout e orts. We introduce in this paper a novel method for ident...
62
Voted
DAC
1997
ACM
15 years 1 months ago
1997
ACM
We present a novel technique CLIP for optimizing both the height and width of CMOS cell layouts in the two-dimensional (2D) style. CLIP is based on integer-linear programming (ILP...
DAC
1999
ACM
15 years 10 months ago
1999
ACM
Recently, several algorithms for interconnect optimization via repeater insertion and wire sizing have appeared based on the Elmore delay model. Using the Devgan noise metric [6] ...
FPGA
1998
ACM
15 years 1 months ago
1998
ACM
In this paper, we present an algorithm for circuit partitioning with complex resource constraints in large FPGAs. Traditional partitioning methods estimate the capacity of an FPGA...
DAC
2007
ACM
15 years 1 months ago
2007
ACM
This paper presents MOJITO, a system which optimizes across thousands of analog circuit topologies simultaneously, and returns a set of sized topologies that collectively provide ...