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180
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IPPS
2005
IEEE
15 years 10 months ago
A Compiler Method for Memory-Conscious Mapping of Applications on Coarse-Grained Reconfigurable Architectures
This paper presents a compiler methodology for memoryaware mapping on 2-Dimensional coarse-grained reconfigurable architectures that aims in improving the mapped applications’ p...
Grigoris Dimitroulakos, Michalis D. Galanis, Costa...
ICPP
2009
IEEE
15 years 11 months ago
Perfomance Models for Blocked Sparse Matrix-Vector Multiplication Kernels
—Sparse Matrix-Vector multiplication (SpMV) is a very challenging computational kernel, since its performance depends greatly on both the input matrix and the underlying architec...
Vasileios Karakasis, Georgios I. Goumas, Nectarios...
183
Voted
IJNS
2000
130views more  IJNS 2000»
15 years 4 months ago
A Programmable VLSI Filter Architecture for Application in Real-Time Vision Processing Systems
An architecture is proposed for the realization of real-time edge-extraction filtering operation in an Address-Event-Representation (AER) vision system. Furthermore, the approach ...
Teresa Serrano-Gotarredona, Andreas G. Andreou, Be...
IDEAL
2004
Springer
15 years 10 months ago
Stock Trading by Modelling Price Trend with Dynamic Bayesian Networks
We study a stock trading method based on dynamic bayesian networks to model the dynamics of the trend of stock prices. We design a three level hierarchical hidden Markov model (HHM...
Jangmin O, Jae Won Lee, Sung-Bae Park, Byoung-Tak ...
139
Voted
ICASSP
2010
IEEE
15 years 5 months ago
Power law discounting for n-gram language models
We present an approximation to the Bayesian hierarchical PitmanYor process language model which maintains the power law distribution over word tokens, while not requiring a comput...
Songfang Huang, Steve Renals