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PDP
2009
IEEE
16 years 1 months ago
A Parallel Implementation of the 2D Wavelet Transform Using CUDA
There is a multicore platform that is currently concentrating an enormous attention due to its tremendous potential in terms of sustained performance: the NVIDIA Tesla boards. The...
Joaquín Franco, Gregorio Bernabé, Ju...
IEEEPACT
2009
IEEE
16 years 25 days ago
Interprocedural Load Elimination for Dynamic Optimization of Parallel Programs
Abstract—Load elimination is a classical compiler transformation that is increasing in importance for multi-core and many-core architectures. The effect of the transformation is ...
Rajkishore Barik, Vivek Sarkar
GLVLSI
2000
IEEE
145views VLSI» more  GLVLSI 2000»
15 years 10 months ago
CMOS system-on-a-chip voltage scaling beyond 50nm
† The limits on CMOS energy dissipation imposed by subthreshold leakage currents and by wiring capacitance are investigated for CMOS generations beyond 50nm at NTRS projected loc...
Azeez J. Bhavnagarwala, Blanca Austin, Ashok Kapoo...
ASMTA
2010
Springer
192views Mathematics» more  ASMTA 2010»
15 years 4 months ago
Packet Loss Minimization in Load-Balancing Switch
Due to the overall growing demand on the network resources and tight restrictions on the power consumption, the requirements to the long-term scalability, cost and performance capa...
Yury Audzevich, Levente Bodrog, Yoram Ofek, Mikl&o...
VEE
2010
ACM
218views Virtualization» more  VEE 2010»
16 years 1 months ago
Improving compiler-runtime separation with XIR
Intense research on virtual machines has highlighted the need for flexible software architectures that allow quick evaluation of new design and implementation techniques. The inte...
Ben Titzer, Thomas Würthinger, Doug Simon, Ma...