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» Hierarchical Placement and Network Design Problems
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DAC
2011
ACM
13 years 11 months ago
Fault-tolerant 3D clock network
Clock tree synthesis is one of the most important and challenging problems in 3D ICs. The clock signals have to be delivered by through-silicon vias (TSVs) to different tiers with...
Chiao-Ling Lung, Yu-Shih Su, Shih-Hsiu Huang, Yiyu...
WIDM
2004
ACM
15 years 5 months ago
XPath lookup queries in P2P networks
We address the problem of querying XML data over a P2P network. In P2P networks, the allowed kinds of queries are usually exact-match queries over file names. We discuss the exte...
Angela Bonifati, Ugo Matrangolo, Alfredo Cuzzocrea...
SIGCOMM
1998
ACM
15 years 3 months ago
An Active Service Framework and Its Application to Real-Time Multimedia Transcoding
Several recent proposals for an “active networks” architecture advocate the placement of user-defined computation within the network as a key mechanism to enable a wide range...
Elan Amir, Steven McCanne, Randy H. Katz
ICCAD
2006
IEEE
126views Hardware» more  ICCAD 2006»
15 years 8 months ago
Optimizing yield in global routing
We present the first efficient approach to global routing that takes spacing-dependent costs into account and provably finds a near-optimum solution including these costs. We sh...
Dirk Müller
105
Voted
ASPDAC
2009
ACM
108views Hardware» more  ASPDAC 2009»
15 years 6 months ago
Synthesis of networks on chips for 3D systems on chips
Three-dimensional stacking of silicon layers is emerging as a promising solution to handle the design complexity and heterogeneity of Systems on Chips (SoCs). Networks on Chips (N...
Srinivasan Murali, Ciprian Seiculescu, Luca Benini...