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EURODAC
1990
IEEE
73views VHDL» more  EURODAC 1990»
15 years 6 months ago
A new method for the state reduction of incompletely specified finite sequential machines
Maria J. Avedillo, José M. Quintana, Jos&ea...
73
Voted
FORMATS
2006
Springer
15 years 5 months ago
Simulator for Real-Time Abstract State Machines
Pavel Vasilyev
APAQS
2001
IEEE
15 years 5 months ago
Testable Use Cases in the Abstract State Machine Language
Wolfgang Grieskamp, Markus Lepper, Wolfram Schulte...
100
Voted
FASE
2000
Springer
15 years 5 months ago
Analysing UML Active Classes and Associated State Machines - A Lightweight Formal Approach
Gianna Reggio, Egidio Astesiano, Christine Choppy,...