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ECBS
1996
IEEE
155views Hardware» more  ECBS 1996»
15 years 5 months ago
Model-Integrated Program Synthesis Environment
In this paper, it is shown that, through the use of Model-Integrated Program Synthesis MIPS, parallel real-time implementations of image processing data ows can be synthesized fro...
Janos Sztipanovits, Gabor Karsai, Hubertus Franke
120
Voted
CASES
2005
ACM
15 years 2 months ago
Exploiting pipelining to relax register-file port constraints of instruction-set extensions
Customisable embedded processors are becoming available on the market, thus making it possible for designers to speed up execution of applications by using Application-specific F...
Laura Pozzi, Paolo Ienne
AVI
2006
15 years 2 months ago
Mobility agents: guiding and tracking public transportation users
Increasingly, public transportation systems are equipped with Global Positioning Systems (GPS) connected to control centers through wireless networks. Controllers use this infrast...
Alexander Repenning, Andri Ioannidou
99
Voted
TASE
2008
IEEE
15 years 22 days ago
Lean Buffering in Serial Production Lines With Nonidentical Exponential Machines
Lean buffering is the smallest buffer capacity, which is necessary and sufficient to ensure the desired production rate of a manufacturing system. Literature offers methods for des...
Shu-Yin Chiang, Alexander Hu, Semyon M. Meerkov
HIPEAC
2011
Springer
14 years 14 days ago
NoC-aware cache design for multithreaded execution on tiled chip multiprocessors
In chip multiprocessors (CMPs), data accesslatency dependson the memory hierarchy organization, the on-chip interconnect (NoC), and the running workload. Reducing data access late...
Ahmed Abousamra, Alex K. Jones, Rami G. Melhem