34 search results - page 5 / 7 » High Density Through Silicon Via (TSV) |
ISCA
2010
IEEE
15 years 2 months ago
2010
IEEE
The performance of future manycore processors will only scale with the number of integrated cores if there is a corresponding increase in memory bandwidth. Projected scaling of el...
NOCS
2009
IEEE
15 years 4 months ago
2009
IEEE
Design Constraints imposed by global interconnect delays as well as limitations in integration of disparate technologies make 3-D chip stacks an enticing technology solution for m...
ICCAD
2006
IEEE
15 years 6 months ago
2006
IEEE
- Redundant via insertion and line end extension employed in the post-routing stage are two well known and highly recommended techniques to reduce yield loss due to via failure. Ho...
DATE
2009
IEEE
15 years 4 months ago
2009
IEEE
— Heat removal and power delivery are two major reliability concerns in the 3D stacked IC technology. Liquid cooling based on micro-fluidic channels is proposed as a viable solu...
ICCAD
2005
IEEE
15 years 6 months ago
2005
IEEE
Future inter- and intra-ULSI interconnect systems demand extremely high data rates as well as bi-directional multi-I/O concurrent service, re-configurable computing/processing arc...