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ISQED
2010
IEEE
141views Hardware» more  ISQED 2010»
15 years 4 months ago
Assessing chip-level impact of double patterning lithography
—Double patterning lithography (DPL) provides an attractive alternative or a supplementary method to enable the 32nm and 22nm process nodes, relative to costlier technology optio...
Kwangok Jeong, Andrew B. Kahng, Rasit Onur Topalog...
ICSE
2004
IEEE-ACM
15 years 10 months ago
A Framework for Ensuring and Improving Dependability in Highly Distributed Systems
A distributed software system's deployment architecture can have a significant impact on the system's dependability. Dependability is a function of various system paramet...
Sam Malek, Nels Beckman, Marija Mikic-Rakic, Nenad...
APL
1993
ACM
15 years 1 months ago
The Role of APL and J in High-Performance Computation
Although multicomputers are becoming feasible for solving large problems, they are difficult to program: Extraction of parallelism from scalar languages is possible, but limited....
Robert Bernecky
ACSC
2009
IEEE
15 years 4 months ago
The Impact of Quanta on the Performance of Multi-level Time Sharing Policy under Heavy-tailed Workloads
Recent research indicates that modern computer workloads (e.g. processing time of web requests) follow heavy-tailed distributions. In a heavy-tailed distribution there are a large...
Malith Jayasinghe, Zahir Tari, Panlop Zeephongseku...
HPCA
2000
IEEE
15 years 2 months ago
Impact of Chip-Level Integration on Performance of OLTP Workloads
With increasing chip densities, future microprocessor designs have the opportunity to integrate many of the traditional systemlevel modules onto the same chip as the processor. So...
Luiz André Barroso, Kourosh Gharachorloo, A...