31 search results - page 1 / 7 » High Level Synthesis of Pipelined Instruction Set Processors... |
DAC
1992
ACM
15 years 3 months ago
1992
ACM
Designing instruction set processors and constructing their compilers are mutually dependent tasks. Piper is a high level synthesis tool of ADAS which controls the hardware-softwa...
MICRO
1993
IEEE
15 years 3 months ago
1993
IEEE
The conventional classification of inter-instruction dependencies (data, anti and output dependencies) provides a basic scheme for the analysis of pipeline hazards in pipelined in...
102
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ATS
2004
IEEE
15 years 3 months ago
2004
IEEE
TIS (Test Instruction Set) is an instruction level technique for CPU core self-testing. This method is based on enhancing a CPU instruction set with test instructions. TIS replace...
100
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DATE
2002
IEEE
15 years 4 months ago
2002
IEEE
The design of application (-domain) specific instructionset processors (ASIPs), optimized for code size, has traditionally been accompanied by the necessity to program assembly, ...
125
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LCTRTS
2007
Springer
15 years 5 months ago
2007
Springer
Industry’s demand for flexible embedded solutions providing high performance and short time-to-market has led to the development of configurable and extensible processors. The...