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SASP
2009
IEEE
291views Hardware» more  SASP 2009»
15 years 9 months ago
FCUDA: Enabling efficient compilation of CUDA kernels onto FPGAs
— As growing power dissipation and thermal effects disrupted the rising clock frequency trend and threatened to annul Moore’s law, the computing industry has switched its route...
Alexandros Papakonstantinou, Karthik Gururaj, John...
ISSS
1995
IEEE
161views Hardware» more  ISSS 1995»
15 years 6 months ago
Synthesis of pipelined DSP accelerators with dynamic scheduling
To construct complete systems on silicon, application speci c DSP accelerators are needed to speed up the execution of high throughput DSP algorithms. In this paper, a methodology...
Patrick Schaumont, Bart Vanthournout, Ivo Bolsens,...
IPPS
1997
IEEE
15 years 7 months ago
Modeling Compiled Communication Costs in Multiplexed Optical Networks
Improvements in optical technology will enable the constructionof high bandwidth, low latencyswitching networks. These networks have many applications in massively parallel proces...
Charles A. Salisbury, Rami G. Melhem
MICRO
1991
IEEE
85views Hardware» more  MICRO 1991»
15 years 6 months ago
Comparing Static and Dynamic Code Scheduling for Multiple-Instruction-Issue Processors
This paper examines two alternative approaches to supporting code scheduling for multiple-instruction-issue processors. One is to provide a set of non-trapping instructions so tha...
Pohua P. Chang, William Y. Chen, Scott A. Mahlke, ...
HIPEAC
2007
Springer
15 years 9 months ago
Compiler-Assisted Memory Encryption for Embedded Processors
A critical component in the design of secure processors is memory encryption which provides protection for the privacy of code and data stored in off-chip memory. The overhead of ...
Vijay Nagarajan, Rajiv Gupta, Arvind Krishnaswamy