Sciweavers

2852 search results - page 109 / 571
» High Performance Architectures and Compilers
Sort
View
ICCAD
2004
IEEE
100views Hardware» more  ICCAD 2004»
16 years 1 days ago
DynamoSim: a trace-based dynamically compiled instruction set simulator
Instruction set simulators are indispensable tools for the architectural exploration and verification of embedded systems. Different techniques have recently been proposed to spe...
Massimo Poncino, Jianwen Zhu
ISSAC
2007
Springer
128views Mathematics» more  ISSAC 2007»
15 years 9 months ago
Productivity and performance using partitioned global address space languages
Partitioned Global Address Space (PGAS) languages combine the programming convenience of shared memory with the locality and performance control of message passing. One such langu...
Katherine A. Yelick, Dan Bonachea, Wei-Yu Chen, Ph...
HPN
1992
15 years 4 months ago
A Host Interface Architecture for High-Speed Networks
This paper describes a new host interface architecture for high-speed networks operating at 800 of Mbit/second or higher rates. The architecture is targeted to achieve several 100...
Peter Steenkiste, Brian Zill, H. T. Kung, Steven S...
136
Voted
PLDI
2003
ACM
15 years 8 months ago
A compiler framework for speculative analysis and optimizations
Speculative execution, such as control speculation and data speculation, is an effective way to improve program performance. Using edge/path profile information or simple heuristi...
Jin Lin, Tong Chen, Wei-Chung Hsu, Pen-Chung Yew, ...
115
Voted
LCTRTS
2010
Springer
15 years 10 months ago
Operation and data mapping for CGRAs with multi-bank memory
Coarse Grain Reconfigurable Architectures (CGRAs) promise high performance at high power efficiency. They fulfil this promise by keeping the hardware extremely simple, and movi...
Yongjoo Kim, Jongeun Lee, Aviral Shrivastava, Yunh...