2852 search results - page 111 / 571 » High Performance Architectures and Compilers |
104
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ICCD
2006
IEEE
16 years 2 days ago
2006
IEEE
— A reduced complexity LDPC decoding method is presented that dramatically reduces wire interconnect complexity, which is a major issue in LDPC decoders. The proposed Split-Row m...
117
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MICRO
2003
IEEE
15 years 8 months ago
2003
IEEE
Wire delays are a major concern for current and forthcoming processors. One approach to attack this problem is to divide the processor into semi-independent units referred to as c...
144
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HOTI
2005
IEEE
15 years 8 months ago
2005
IEEE
: The exposed memory hierarchies employed in many network processors (NPs) are expensive in terms of meeting the worst-case processing requirement. Moreover, it is difficult to ef...
106
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LFP
1994
15 years 4 months ago
1994
This paper describes an implementation of the new Scheme multiple values interface. The implementation handles multiple values efficiently, with no run-time overhead for normal ca...
134
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ICPP
1998
IEEE
15 years 7 months ago
1998
IEEE
To execute a shared memory program efficiently, we have to manage memory consistency with low overheads, and have to utilize communication bandwidth of the platform as much as pos...