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ISCAS
2002
IEEE
124views Hardware» more  ISCAS 2002»
15 years 8 months ago
Performance optimization of multiple memory architectures for DSP
Multiple memory module architecture offers higher performance by providing potentially doubled memory bandwidth. Two key problems in gaining high performance in this kind of archi...
Qingfeng Zhuge, Bin Xiao, Edwin Hsing-Mean Sha
HPCA
2003
IEEE
16 years 3 months ago
Evaluating the Impact of Communication Architecture on the Performability of Cluster-Based Services
We consider the impact of different communication architectures on the performability (performance + availability) of cluster-based servers. In particular, we use a combination of ...
Kiran Nagaraja, Neeraj Krishnan, Ricardo Bianchini...
EVOW
2008
Springer
15 years 5 months ago
Architecture Performance Prediction Using Evolutionary Artificial Neural Networks
The design of computer architectures requires the setting of multiple parameters on which the final performance depends. The number of possible combinations make an extremely huge ...
Pedro A. Castillo, Antonio Miguel Mora, Juan Juli&...
VLSID
2004
IEEE
107views VLSI» more  VLSID 2004»
16 years 3 months ago
Performance Analysis of Inter Cluster Communication Methods in VLIW Architecture
With increasing demands for high performance by embedded systems, especially by digital signal processing applications, embedded processors must increase available instruction lev...
Sourabh Saluja, Anshul Kumar
ISCA
1995
IEEE
118views Hardware» more  ISCA 1995»
15 years 6 months ago
The EM-X Parallel Computer: Architecture and Basic Performance
Latency tolerance is essential in achieving high performance on parallel computers for remote function calls and fine-grained remote memory accesses. EM-X supports interprocessor ...
Yuetsu Kodama, Hirohumi Sakane, Mitsuhisa Sato, Ha...