2852 search results - page 126 / 571 » High Performance Architectures and Compilers |
130
Voted
MICRO
2008
IEEE
15 years 9 months ago
2008
IEEE
—Caches ideally should have low miss rates and short access times, and should be power efficient at the same time. Such design goals are often contradictory in practice. Recent f...
127
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ICS
1999
Tsinghua U.
15 years 7 months ago
1999
Tsinghua U.
The Virtual Interface (VI) Architecture provides protected userlevel communication with high delivered bandwidth and low permessage latency, particularly for small messages. The V...
118
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EUROPAR
2009
Springer
15 years 7 months ago
2009
Springer
Multicore architectures featuring specialized accelerators are getting an increasing amount of attention, and this success will probably influence the design of future High Perfor...
131
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SPAA
2010
ACM
15 years 3 months ago
2010
ACM
We present a scheduling algorithm of stream programs for multi-core architectures called team scheduling. Compared to previous multi-core stream scheduling algorithms, team schedu...
116
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ISCA
1998
IEEE
15 years 7 months ago
1998
IEEE
Explicitly Parallel Instruction Computing (EPIC) architectures require the compiler to express program instruction level parallelism directly to the hardware. EPIC techniques whic...