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ISCA
2000
IEEE
156views Hardware» more  ISCA 2000»
15 years 7 months ago
CHIMAERA: a high-performance architecture with a tightly-coupled reconfigurable functional unit
Reconfigurable hardware has the potential for significant performance improvements by providing support for applicationāˆ’specific operations. We report our experience with Chimae...
Zhi Alex Ye, Andreas Moshovos, Scott Hauck, Prithv...
ISCA
1999
IEEE
96views Hardware» more  ISCA 1999»
15 years 7 months ago
PipeRench: A Coprocessor for Streaming multimedia Acceleration
Future computing workloads will emphasize an architecture's ability to perform relatively simple calculations on massive quantities of mixed-width data. This paper describes ...
Seth Copen Goldstein, Herman Schmit, Matthew Moe, ...
ICMCS
2006
IEEE
121views Multimedia» more  ICMCS 2006»
15 years 9 months ago
Acoustic Echo Cancelation for High Noise Environments
Acoustic echo cancellation (AEC) is highly imperative for enhanced communication in noisy environments such as a car or a conference room. In this work, we present a dualstructure...
Amit Chhetri, Jack W. Stokes, Dinei A. F. Flor&eci...
ASPLOS
1996
ACM
15 years 7 months ago
The Structure and Performance of Interpreters
Interpreted languages have become increasingly popular due to demands for rapid program development, ease of use, portability, and safety. Beyond the general impression that they ...
Theodore H. Romer, Dennis Lee, Geoffrey M. Voelker...
IPPS
2009
IEEE
15 years 10 months ago
Scalable RDMA performance in PGAS languages
Partitioned Global Address Space (PGAS) languages provide a unique programming model that can span shared-memory multiprocessor (SMP) architectures, distributed memory machines, o...
Montse Farreras, George Almási, Calin Casca...