2852 search results - page 156 / 571 » High Performance Architectures and Compilers |
108
Voted
USENIX
2004
15 years 4 months ago
2004
This paper evaluates techniques for improving the performance of three architecturally different web servers. We study strategies for effectively accepting incoming connections un...
125
Voted
ISCAS
2007
IEEE
15 years 9 months ago
2007
IEEE
—In this paper, we propose a high speed adder which is adopted for our reconfigurable architecture called FleXilicon. To support sub-word parallelism, the FleXilicon architecture...
140
Voted
ICASSP
2011
IEEE
14 years 7 months ago
2011
IEEE
In this paper, based on the proposed parallelization scheme of binary arithmetic decoding, a parallel AVC/H.264 context-based adaptive binary arithmetic coding (CABAC) decoder wit...
141
Voted
SBCCI
2005
ACM
15 years 9 months ago
2005
ACM
The Voltage Controlled Oscillator (VCO) is a fundamental block in RF IC architectures. Today’s wireless communication applications do require a high level of performances from s...
141
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ASAP
2003
IEEE
15 years 8 months ago
2003
IEEE
At the Leiden Embedded Research Center, we are developing a compiler called Compaan that automatically translates signal processing applications written in Matlab into Kahn Proces...