Sciweavers

2852 search results - page 164 / 571
» High Performance Architectures and Compilers
Sort
View
155
Voted
ISCA
1993
IEEE
125views Hardware» more  ISCA 1993»
15 years 7 months ago
Evaluation of Mechanisms for Fine-Grained Parallel Programs in the J-Machine and the CM-5
er uses an abstract machine approach to compare the mechanisms of two parallel machines: the J-Machine and the CM-5. High-level parallel programs are translated by a single optimi...
Ellen Spertus, Seth Copen Goldstein, Klaus E. Scha...
122
Voted
SAC
2008
ACM
15 years 2 months ago
Optimizing code through iterative specialization
Code specialization is a way to obtain significant improvement in the performance of an application. It works by exposing values of different parameters in source code. The availa...
Minhaj Ahmad Khan, Henri-Pierre Charles, Denis Bar...
MICRO
2007
IEEE
184views Hardware» more  MICRO 2007»
15 years 9 months ago
Data Access Partitioning for Fine-grain Parallelism on Multicore Architectures
The recent design shift towards multicore processors has spawned a significant amount of research in the area of program parallelization. The future abundance of cores on a singl...
Michael L. Chu, Rajiv A. Ravindran, Scott A. Mahlk...
141
Voted
CODES
2001
IEEE
15 years 7 months ago
Compiler-directed selection of dynamic memory layouts
Compiler technology is becoming a key component in the design of embedded systems, mostly due to increasing participation of software in the design process. Meeting system-level ob...
Mahmut T. Kandemir, Ismail Kadayif
158
Voted
DSD
2010
IEEE
190views Hardware» more  DSD 2010»
15 years 3 months ago
Hardware-Based Speed Up of Face Recognition Towards Real-Time Performance
— Real-time face recognition by computer systems is required in many commercial and security applications because it is the only way to protect privacy and security in the sea of...
I. Sajid, Sotirios G. Ziavras, M. M. Ahmed